VHDL

Materiais de aulas 2016 1º Semestre

  • Slides aula 1 – Prof. Thiago PDF incluso em 16/03/2016
  • Slides aula 2 – Prof. Thiago PDF incluso em 16/03/2016
  • Slides aula 3 – Prof. Thiago PDF incluso em 20/04/2016
  • Slides aula 4 – Prof. Thiago PDF incluso em 20/04/2016
  • Material aula 5 e 6 – PDF incluso 11/05/2016
  • Material Aula 6 – PDF uso de componente e For incluso dia 18/05/2016
  • Descrição do trabalho B2 – incluso dia 11/05/2016

Mapa de Pinos para Ciclone II arquivo em excel

Tutorial de gravação no Kit  By Prof. Saulo

Manual Ciclone II

 

Material extra:

EXEMPLO DISPLAY NO laboratório dia 07/05/16

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY display7seg IS
PORT (
SW0, SW1, SW2, SW3: IN BIT;
HEX0 :OUT BIT_VECTOR (6 DOWNTO 0));
END display7seg;

ARCHITECTURE equacoesPortas OF display7seg IS
SIGNAL DECIMAL : BIT_VECTOR(3 DOWNTO 0);
BEGIN
DECIMAL <= SW3 & SW2 & SW1 & SW0;
PROCESS (SW0, SW1, SW2, SW3)
BEGIN
IF DECIMAL = “0000” THEN HEX0 <= “1000000”;
ELSIF DECIMAL = “0001” THEN HEX0 <= “1111001”;
ELSIF DECIMAL = “0010” THEN HEX0 <= “0100100”;
ELSIF DECIMAL = “0011” THEN HEX0 <= “0110000”;
ELSIF DECIMAL = “0100” THEN HEX0 <= “0011001”;
ELSIF DECIMAL = “0101” THEN HEX0 <= “0010010”;
ELSIF DECIMAL = “0110” THEN HEX0 <= “0000010”;
ELSIF DECIMAL = “0111” THEN HEX0 <= “1111000”;
ELSIF DECIMAL = “1000” THEN HEX0 <= “0000000”;
ELSE HEX0 <= “0011000”;
END IF;
END PROCESS;
END equacoesPortas;

 

 

v2.2

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY display7seg IS
PORT (
SW: BIT_VECTOR (3 DOWNTO 0);
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 :OUT BIT_VECTOR (6 DOWNTO 0) :=”1111111″);
END display7seg;

ARCHITECTURE imprimeDisplay OF display7seg IS
–gfedcba
CONSTANT N0 :BIT_VECTOR (6 DOWNTO 0) := “1000000”; –0
CONSTANT N1 :BIT_VECTOR (6 DOWNTO 0) := “1111001”; –1
CONSTANT N2 :BIT_VECTOR (6 DOWNTO 0) := “0100100”; –2
CONSTANT N3 :BIT_VECTOR (6 DOWNTO 0) := “0110000”; –3
CONSTANT N4 :BIT_VECTOR (6 DOWNTO 0) := “0011001”; –4
CONSTANT N5 :BIT_VECTOR (6 DOWNTO 0) := “0010010”; –5
CONSTANT N6 :BIT_VECTOR (6 DOWNTO 0) := “0000010”; –6
CONSTANT N7 :BIT_VECTOR (6 DOWNTO 0) := “1111000”; –7
CONSTANT N8 :BIT_VECTOR (6 DOWNTO 0) := “0000000”; –8
CONSTANT N9 :BIT_VECTOR (6 DOWNTO 0) := “0011000”; –9
CONSTANT NA :BIT_VECTOR (6 DOWNTO 0) := “0001000”; –A
CONSTANT NB :BIT_VECTOR (6 DOWNTO 0) := “0000011”; –B
CONSTANT NC :BIT_VECTOR (6 DOWNTO 0) := “1000110”; –C
CONSTANT ND :BIT_VECTOR (6 DOWNTO 0) := “0100001”; –D
CONSTANT NE :BIT_VECTOR (6 DOWNTO 0) := “0000110”; –E
CONSTANT NF :BIT_VECTOR (6 DOWNTO 0) := “0001110”; –F

SIGNAL displayHex : BIT_VECTOR(3 DOWNTO 0);

BEGIN
displayHex <= SW;
PROCESS (SW)
BEGIN
IF displayHex = “0000” THEN HEX0 <= N0;
ELSIF displayHex = “0001” THEN HEX0 <= N1;
ELSIF displayHex = “0010” THEN HEX0 <= N2;
ELSIF displayHex = “0011” THEN HEX0 <= N3;
ELSIF displayHex = “0100” THEN HEX0 <= N4;
ELSIF displayHex = “0101” THEN HEX0 <= N5;
ELSIF displayHex = “0110” THEN HEX0 <= N6;
ELSIF displayHex = “0111” THEN HEX0 <= N7;
ELSIF displayHex = “1000” THEN HEX0 <= N8;
ELSIF displayHex = “1001” THEN HEX0 <= N9;
ELSIF displayHex = “1010” THEN HEX0 <= NA;
ELSIF displayHex = “1011” THEN HEX0 <= NB;
ELSIF displayHex = “1100” THEN HEX0 <= NC;
ELSIF displayHex = “1101” THEN HEX0 <= ND;
ELSIF displayHex = “1110” THEN HEX0 <= NE;
ELSE HEX0 <= NF;
END IF;

IF displayHex = “0000” THEN HEX3 <= N0;
ELSIF displayHex = “0001” THEN HEX3 <= N9;
ELSIF displayHex = “0010” THEN HEX3 <= N2;
ELSIF displayHex = “0011” THEN HEX3 <= NA;
ELSIF displayHex = “0100” THEN HEX3 <= NB;
ELSIF displayHex = “0101” THEN HEX3 <= NC;
ELSIF displayHex = “0110” THEN HEX3 <= ND;
ELSIF displayHex = “0111” THEN HEX3 <= NE;
ELSIF displayHex = “1000” THEN HEX3 <= NF;
ELSE HEX3 <= N0; –9
END IF;
END PROCESS;
END imprimeDisplay;

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